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005 20231123120909.0
008 230822b |||||||| |||| 00| 0 eng d
020 _a9780470900550
040 _cCUCoM
082 _222
_a600.01 FER
100 _aFerdjallah,Mohammed
_912275
245 _aINTRODUCTION TO DIGITAL SYSTEM
_bModling, synthesis, and simulation using VHDL
_cMohammed Ferdjallah
250 _arev.ed.
260 _aCanada:
_bJohn Wiley and Sons, Inc.,
_c2011
300 _ax,225p.:
_bill.
500 _aIncludes index
650 0 _aEducation
_vTechnology
_912279
856 _uhttp://41.59.100.242:80/cgi-bin/koha/opac-retrieve-file.pl?id=e7693f7e7e54e65e24298f3e4c1ba0bd
942 _2ddc
_cEBKS
999 _c27906
_d27906